1. Field of the Invention
The present invention relates to a preparation method of an exposure original plate such as a photo mask and a reticle, and more particularly to a preparation method of forming a required pattern on the original plate by means of an electron beam (referred to as EB hereinafter) exposure.
2. Description of the Prior Art
The preparation of an exposure original plate such as a photo mask and a reticle by the EB exposure technology is accomplished by irradiating an EB sensitive resist formed on a transparent substrate with EBs in a required pattern using an EB exposure system. In the irradiation of EBs in the required pattern, there exists a technology of scanning the EB sensitive resist with one or a plurality of EBs, or a technology of irradiating the EB sensitive resist with an EB or EBs with its cross section formed in a rectangular form. In either case, it is necessary to prepare exposure data corresponding to a desired pattern to be formed, and carry out EB scanning or exposure using the EB exposure system based on the exposure data.
In the preparation of the EB exposure data, the pattern of the exposure original plate is subdivided into a plurality of rectangular patterns, and data processing is executed by recognizing individual divided rectangular patterns. In the data processing, the so-called optical proximity effect correction (OPC), which corrects the pattern for each part by taking the optical proximity effect into account, is employed, where a technique of a bias method or an inner serif method is available. These are technologies which correct parts of the shape of an object pattern by finding the correlations between the shapes of adjacent patterns, the dimensions between the patterns, and the like. For example, in the bias method, when proximity patterns P2 and P3 exist in parts of a linear wiring pattern P1, as shown in FIG. 14A, a wiring pattern in which part of each side of the wiring pattern P1 is deleted to reduce the pattern width according to the OPC as shown in FIG. 14B, is prepared in order to prevent short-circuiting between these patterns in the pattern formed on the exposure original plate, and EB exposure data corresponding to the corrected pattern are generated. In the meantime, in the inner serif method, when a gate electrode pattern P4 for a MOS transistor is bent in U-shape on both sides of a source-drain region SD, for example, as shown in FIG. 15A, in order to prevent an increase in the gate electrode dimension (gate electrode length) as shown by a broken line in the figure in the connection parts between the bent patterns P42, P43 on both sides and the central rectangular pattern P41, gate electrode pattern in which the inner side of the connection part is deleted to reduce the gate electrode length of the connection part, is created as shown in FIG. 15B, and EB exposure data corresponding to the corrected pattern are prepared.
However, with such a pattern correction by OPC, a problem arises in that micro patterns are generated when the corrected pattern is divided into rectangular patterns. Namely, in the case of the wiring pattern P1 in which portions located close to the proximity patterns are partially removed by the bias method as shown in FIG. 14B, division into a plurality of rectangular patterns P10, P11 and P12 as shown in FIG. 14C generates a rectangular pattern P10 with extremely small width direction size in the portion left by the removal, which becomes a micro pattern. In addition, in the case of the gate electrode pattern P4 by which U-shaped bent part is removed by the inner serif method as shown in FIG. 15B, rectangular patterns P44, P45 and P46 with extremely small size in respective width directions are generated in the regions across the removed portions as shown in FIG. 15C, which become micro patterns.
In recognizing the divided individual rectangular patterns, EB exposure data are prepared by regarding even such a micro pattern, recognized as a micro pattern, as an independent pattern, and EB exposure is carried out based on the obtained EB exposure data. In this case, in the EB exposure method using the point beam raster scan method which EB exposes a required pattern while continuously scanning a mask original plate with an EB of minute beam diameter among EB exposure methods, since the diameter of the EB beam can be reduced to about 0.08 μm, it is possible to expose properly a minute pattern of 0.1 μm. However, since a graphic is deleted in the units of about 0.004 μm in the bias method, rounding in the exposed image occurs at the minimum grid of the diameter of the EB beam. Accordingly, the point beam raster scan method is not applicable to the bias method.
In the meantime, when the exposure method using the variable shaped beam vector scan system (referred to as variable shaped beam exposure method hereinafter) is employed as the EB exposure method, since the current minimum grid is 0.002 μm, the problem of rounding will not occur, but there may arise a case in which it is not possible to EB expose a micro pattern as a normal pattern. The variable shaped beam exposure method is a technology in which EB beams are formed into a rectangular beam of required size by an aperture, further reducing it to an EB of beam bundle with a minute rectangle by a reduction lens, and expose an exposure original plate with the reduced EB. Because of this, assuming that beam blur due to optical proximity effect in the periphery of the rectangular bundle of EB is generated at a width of, for example, about 0.1 μm, the effect of the optical proximity effect on the pattern is inevitable when the size of at least one of the sides of the micro pattern is less than 0.1 μm, and it becomes impossible to normally expose a micro pattern. As a result, pattern defects arise in a pattern of prepared exposure original plate, and if a semiconductor device is manufactured using an exposure original plate with such pattern defects, abnormality in the characteristics of the semiconductor device will occur.
For example, when the pattern is divided into rectangular patterns as in FIG. 14C, the micro pattern P1O fails to be exposed normally as shown in FIG. 14D, with the wiring width of the wiring pattern P1 becoming thin at the intermediate part, the wiring resistance is increased or the wiring is disconnected. In the case of the gate pattern P4 in FIG. 15 B, the micro patterns P44, P45 and P46 generated by the division as shown in FIG. 15C fail to be exposed properly, and a gate electrode is formed with the width size, namely the gate electrode length, being especially small in the pattern P41, as shown in FIG. 15D. Accordingly, when micro patterns are generated in the execution of the bias method or the inner serif method, in order to preclude anomalies in the characteristics of the semiconductor device caused by such pattern defects in the exposure original plate, it has been conventional to withdraw the correction portions of the pattern so as to eliminate the micro patterns and to introduce a processing for reinstating the original pattern. As a result, effective use of the bias method or the inner serif method failed, and in that sense elimination of the drawback in the exposure original plate could not be realized.
In Japanese Patent Applications Laid Open, No. 2000-323389 is disclosed a technique, when EB exposure is executed in divided manner, of designing pattern data so as to provide a region where two patterns can be overlapped in a plane, in order to prevent generation of pattern discontinuity in the connection part. However, since this technique is applicable only to a connection part of the patterns and does not apply to micro patterns which do not involve connection with another pattern, such as the micro pattern generated in a part of the pattern by the OPC by the inner serif method as shown in FIG. 15, and is unable to eliminate a drawback due to such a micro pattern.
Moreover, Japanese Patent Applications Laid Open, No. Hei 9-129531 discloses a technique of taking the direction of the pattern division into consideration so as not to generate micro patterns in dividing a pattern into rectangular patterns. Since, however, patterns corrected by the bias method or the inner serif method tend to generate fine irregularities, it is not necessarily possible to prevent the generation of the micro patterns. For example, when the OPC due to the bias method is applied to the edges on the mutually opposite sides, to a linear wiring pattern as shown in FIG. 14, it is inevitable to generate micro patterns in dividing the wiring pattern in either one of longitudinal or lateral direction using the technique described in this disclosure, and it is difficult to eliminate the problem in the above.